A High - performance OC - 12 / OC - 48 Queue Design Prototype forInput - bu ered ATM

Input-bu ered ATM Switches Haoran Duan; J. W. Lockwood, S. M. Kang, and J. D. Will University of Illinois at Urbana{Champaign NSF ERC for Compound Semiconductor Microelectronics Department of Electrical and Computer Engineering and Beckman Institute for Advanced Science and Technology 405 N. Mathews Ave., Urbana, IL 61801, U.S.A. (217) 244-1565 (Voice), (217) 244-8371 (FAX) email: [email protected] WWW: http://ipoint.vlsi.uiuc.edu Abstract This paper presents the design and prototype of an intelligent, 3-Dimensional-Queue (3DQ) for highperformance, scalable, input bu ered ATM switches. 3DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to priority, destination, and virtual connection. It enforces per virtual connection Quality-of-Service (QoS) and eliminates Head-Of-Line (HOL) blocking. Using FieldProgrammable-Gate-Array (FPGA) devices, our prototype hardware can process ATM cells at 622 Mb/s (OC12). Using more aggressive technology (Multi-ChipModule (MCM) and fast GaAs logic), the same 3DQ design can process cells at 2.5 Gb/s (OC-48). Using 3DQ and Matrix-Unit-Cell-Scheduler (MUCS) as essential components, an input-bu ered ATM switch system has been designed, which can achieve near-100% link bandwidth utilization.